The emerging non-volatile memory, mainly depending on the physical state changes of specific materials to complete the representation of information, is different from the traditional electronic devices that control charges. The information they store can be reflected by resistance, phase, magnetism, etc. The external performance of these devices, namely, the current response, is different under the action of the electric field but can be attributed to the change in resistance state, so they are also collectively referred to as resistive switch devices.^[16]

RRAM, also known as memristor in other literature, has been first reported as early as in the 1960s as the reversible resistive effect induced by the electric pulse.^[61,62] However, due to the limitations of semiconductor technological conditions and market demand at that time, it did not receive widespread attention. In 1971, Chua proposed a theoretical model of memristor,^[63] which predicted the existence of such a device whose resistance state will change with the history of the applied voltage. In 2008, HP company prepared an RRAM device based on TiO₂ in experiments,^[59] and firstly connected RRAM with memristor. Usually using a metal–dielectric–metal sandwich structure, as shown in Fig. 1(a), the insulation medium in RRAM can be invertible between high and low resistance states under electric excitation, which are non-volatile. When the reading voltage is applied, the high/low resistance states will have low/high currents flowing through the resistance functional layer, so as to represent the storage information state ‘0’/‘1’. The underlying physical mechanism of resistance switching is usually based on defects,^[28] either anion-based oxygen vacancies^[64] in the insulating layer or cation-based metal ions^[65] injected from the electrodes. Under the action of forward voltage, these random defects form a conductive path through migration or diffusion and when the reverse voltage is applied, the defects will be re-distributed to break the conductive path. As shown in inset of Fig. 1(a), during the set operation, anion from the insulating oxide or cation from the electrode metal will converge into a conductive filament (CF) at a certain positive threshold voltage. The formation of CFs changes the RRAM devices from the high resistance state to the low resistance state. Under a certain negative threshold voltage, the CFs will break so that the RRAM devices change from the low resistance state to the high resistance state through the reset operation.^[28] RRAM can be classified into unipolar^[66] and bipolar^[67] types according to the polarity of the voltage at which the resistance transition occurs. Unipolarity is caused by the Joule heat^[68] prevailing at high currents to blow the conductive filaments. Meanwhile, the dominant factor in bipolar switching is the electric field.^[28] Roughly all of these devices that rely on the migration and diffusion of the defects to change the state of the resistance can be regarded as RRAM.^[16] Up to now, RRAM has been able to achieve a size of less than 2 nm,^[69] the switching speed can be less than 1 ns, and very little energy is required for the programming operations.^[70] Its rich material selection and simple device physics greatly facilitate array integration and three-dimensional stacking.^[15] With the above advantages, RRAM is the most studied memory technology to explore in-memory computing, which has implemented binary and multi-bit computing in digital applications as well as neural network computing^[24] and stochastics computing.^[71] The switching mechanism of RRAM chemically redox reactions and migration determines its potential in stochastic applications. RRAM is the first memory hardware to be made into a crossbar array^[39] to realize a neural network, which has triggered the upsurge of implementing neural network with memory technology.

First proposed by Stanford university’s Ovshinsky in the 1960s,^[72] the phase change materials that make up the PCM mainly exist in chalcogenides (such as GeSbTe^[73] and GeTe^[74]), which can be stabilized in a polycrystalline or amorphous state. Polycrystalline is long-range ordered with low resistivity while amorphous short-range ordered with high resistivity, by which different data can be stored. The structure of PCM is shown in the inset of Fig. 1(b). The phase change material layer is sandwiched between two electrodes, and there is a heating resistance inserted between the bottom electrode and the material layer. In the set operation, a small but long-lasting current generates a high temperature through the device, increasing the temperature of the PCM layer to the crystallization temperature T_c. When the set current is kept long enough for the phase change layer to be gradually crystallization, the low resistance state will be reached after the crystallization is completed. In the reset operation, a large but short duration current passes through the heating resistor to increase the phase change material temperature above the melting point (T_m), making the material become amorphous, then it exhibits a high resistance state. The operation curve is shown in Fig. 1(b). The amorphous portion usually exhibits a “mushroom” shape (Fig. 1(b) inset), which is caused by a pillar-like heating resistor. By optimizing the structure of the heating resistor to control the Joule heat and current, the energy consumption and the miniaturization of the PCM can be further improved.^[75] PCM also has the advantages of simple structure easy to scaling, robust endurance (approximately 10⁹–10¹²),^[76] ultra-fast writing speed (0.7 ns),^[60] and long retention time.^[77,78] Also, the memory window of PCM is large enough to represent multiple states by the degree of crystallization,^[79] thus realizing multiple state storage^[79,80] easily. Since PCM has many similar features to RRAM, the application schemes like binary,^[81,82] stochastic,^[44,49] and crossbar-array^[83–85] computing can also be extended to PCM. A unique feature of PCM is the multiply accumulation due to the thermally induced volume change, with which PCM has good prospects in synaptic and neuronal elements of analog artificial neural networks and multiple state accumulation.^[44,86,87]

MRAM is used for information storage through a magnetic tunnel junction (MTJ).^[88] The unit structure is shown in the inset of Fig. 1(c), which is mainly composed of a free layer, an insulating tunnel layer, and a pinned layer. The tunneling layer, generally MgO₂ or Al₂O₃, is extremely thin to 1 nm, to separate the free layer from the pinned layer. The magnetic domains of the pinned layer are fixed in a certain direction, and the magnetic domains of the free layer can be flipped in direction with the applied magnetic field. When the two ferromagnetic polarizations are parallel, MTJ has a low resistance. Conversely, it has high resistance. After the spin-transfer effect was proposed in 1996,^[89] it has received considerable attention in MRAM again.^[90,91] When the current passes through the pinned layer, the electrons whose spin direction is antiparallel to the pinned layer are reflected more significantly than the electrons whose spin direction is parallel. Consequently, the current will be polarized by spin and maintain this polarization property after passing through the tunneling layer. When arriving at the free layer, the spin angular momentum transfer torque caused by the polarization current can rotate the magnetic polarization. When the current is strong enough and lasts long enough, the magnetization of the free layer is reversed to coincide with the pinned layer. Conversely, if the current first passes through the free layer, the electrons reflected back at the surface of the pinned layer have a different polarization to the pinned layer and rotate the free layer magnetization in the antiparallel state. Therefore, we can reverse the magnetization by current to change the resistance of MTJ (Fig. 1(c)). Such a spin transfer torque mechanism can make MRAM consume less energy and smaller area^[92] while have reliable writing speed as fast as 2 ns^[93] and the endurance up to 10¹⁴,^[94] with a magnetoresistance ratio (namely, the relative change of resistance) up to 200%–300%,^[95] allowing STT-MRAM to be one of the most promising memory technologies. STT-MRAM can be implemented as analog synapses^[96] and logic devices.^[97] A stochastic MTJ inspired by the principles of neural networks reveals that it is probably the best choice to implement a true random number generator.^[98,99]

Traditional flash memory is a considerably mature and highly commercial non-volatile memory that is available everywhere. Flash memory is usually divided into two categories, one is the structure of NAND, which can achieve ultra-high-density storage, but the read/write speed is slower; the other is the NOR structure, which can operate independently for each bit unit and the read/write speed is also faster, but it is relatively large. The basic unit of flash is the floating gate transistor, whose basic structure is shown in the inset of Fig. 1(d). The number of electrons in the floating gate is controlled by applying a suitable voltage pulse. In the write operation, the control gate is applied with a positive voltage, the drain terminal is applied with a high voltage pulse, and the source is grounded. The electrons in the channel get enough energy during the transport to become hot electrons scattered into the floating gate through the oxidation barrier, so that the threshold voltage is increased. In the erasing operation, the control gate is grounded, the drain is floating, and a high voltage pulse is applied to the source, so that the electrons in the floating gate will tunnel into the source region through the oxide barrier, reducing the threshold voltage (Fig. 1(d)).^[100] It is well known that the threshold voltage of the transistor can be changed by injecting or erasing charge into the floating gate, thus distinguishing the different states for storage with the advantages of low cost and high flexibility. Thanks to the maturity of physical tunneling mechanism and commercial preparation, flash can be mass-produced in large scale arrays with high accuracy, high density, high efficiency, and low cost, which is suitable for deep learning and artificial intelligence applications. The structure of the NOR flash memory array is similar to the crossbar array, making it possible for the implementation of matrix-vector multiplication.^[101] Only by modifying the connecting mode of the array and adopting another read–write rules, the amount of charge in the floating gate can be precisely controlled, and flash can realize multi-bit storage. At a suitable source–drain bias, the output current of the flash will be determined by the gate voltage and the stored charge, whose accuracy can be regulated at 1%. In this way, the flash storage unit obtains the drain current through the gate voltage and the storage state, which can be regarded as a multiplication operation. A 3D NAND for computing has also been fabricated, greatly expanding the scalability of the NOR structure.^[102] As long as the design of the peripheral circuit is implemented appropriately, flash can complete the function of in-memory computing efficiently.^[103–105]

FeFET is a combination of traditional transistors and ferroelectric materials.^[106] Due to the spontaneous polarization characteristics of ferroelectric materials, the atoms in the crystal can move over the potential barrier after applying a suitable external field (required to be larger than the coercive field E_c), leading to the inversion of the intrinsic polarization. This characteristic that the spontaneous polarization can change direction with the external electric field is called ferroelectricity. When the electric field is removed, the polarization state can be maintained so the stable passive/negative polarization states can exactly correspond to the values of ‘1’/‘0’ in binary logic, forming a binary switch.^[107] The two stable states can be repeatedly reversed by the electric field, resulting in a hysteresis curve of the polarization on the electric field, as shown in Fig. 1(e), commonly referred to as the hysteresis curve, showing that the magnetic domain remains unchanged after reversal. Therefore, the ferroelectric based memory has the characteristic of non-volatile. When the ferroelectric thin film with ferroelectric polarization is introduced into the transistor gate, the threshold voltage of the transistor will be changed. Taking n-type MOS as an example (Fig. 1(e) inset), when the polarization direction is upward, negative polarization charge is induced on the lower surface of the ferroelectric thin film, which will cause the energy band on the surface of the channel to bend upward, resulting in the positive drift of the threshold voltage. When the polarization direction is downward, the lower surface of the ferroelectric thin film induces the positive polarization charge, which causes the channel surface energy band to bend downward, thus causing the threshold voltage to drift in the negative direction. When the data is written, under the action of positive/negative voltages, the steady-state polarization charge induced in the ferroelectric thin film causes the transistor to have high/low threshold voltages, corresponding to binary date ‘0’/‘1’. When the data is read, the drain current under different threshold voltages can be obtained by applying a voltage on the drain of the transistor so that the ferroelectric polarization direction can be determined according to the magnitude of the drain current, thus corresponding to the stored binary value. Only by adding ferroelectric materials to the traditional transistor process, the storage function can be added based on calculation.^[36,108] Due to the simple structure of the memory cell, one-transistor area, and non-destructive readout, FeFET has attracted extensive attention from researchers. As a memory device similar to flash, FeFET can also be used to construct crossbar neural networks, but with faster read/write speed.^[109,110] Not only the vector-matrix multiplication can be realized naturally by FeFET, but also the STDP and LIF of the SNN can be implemented in FeFET.^[35,111] FeFET has unique advantages of symmetric/linear programming in neuromorphic computation,^[112] requiring only a transistor and a resistor to bionic the basic functions of neurons.^[111]

SRAM memory cell has a variety of structures, such as 4T, 6T, 8T, and 12T, among them, the 6T structure can realize the better performance, thereby the cell structure generally adopts the 6T structure.^[113] As shown in the inset of Fig. 1(f), the six transistors are symmetrically distributed, among which M1–M4 are bistable circuits including two cross-coupled invertors for interlocking and storing one digital signal. M5 and M6, namely, the access transistors, complete the function of connecting or disconnecting the memory unit from the peripheral circuit during the read and write operations. The access of the cell is enabled by the word line (WL). When the WL is at a high level, the access transistor is turned on, the stored value is transferred to the bit line (BL), and the inverse of the value is transmitted to the bit line bar (BLB), so the peripheral circuit reads information through BL and BLB. During the write operation, the peripheral circuit passes the voltage to BL and BLB as inputs, and after the WL is enabled, information is written to the memory cell. Although SRAM occupies a relatively large area, it is the fastest memory close to the computing unit, and is an indispensable part of the processing chip, occupying a considerable area in the chip. In today’s mature processer chips, with a little modification, the computing function like NOR and AND can be directly completed on SRAM,^[114] and the weight value of ± 1 can be stored as a weight node to complete matrix operation.^[34] In a crossbar array of 6T SRAM, the classify mode used for inference has a better static noise margin than the conventional SRAM mode. Dynamic random access memory (DRAM) is another volatile memory that is also available for in-memory computing such as Boolean logic.^[115,116] However, there is no functional demonstration of MVM within DRAM arrays that can convince us DRAM is conducive to efficient parallel computing. While SRAM still consumes a considerable large cell area inside the most advanced chip, DRAM faces even greater scaling difficulties and costs more energy and circuitry for the refresh operation. Unlike SRAM, the technical processes make DRAM further away from the conventional computing and control unit. Combined with the fact that SRAM can be seamlessly integrated with today’s most advanced standard processes for large-scale integration,^[117] SRAM is the more attractive volatile memory technology for in-memory computing.

On the road of device miniaturization, people have found nanoscale materials with new characteristics, such as carbon nanotubes^[118] and two-dimensional materials.^[119] These nanomaterials can not only make transistors smaller in size and continue Moore’s law, but also improve their energy efficiency and speed by orders of magnitude. In addition to the performance improvements, these new materials can also be vertically stacked using their structural advantages for in situ storage above the cell. In Fig. 1(g), an integrated system has four functional layers, including a silicon-based logic layer, a carbon nanotube computing layer, an RRAM storage layer, and a carbon nanotube sensing layer.^[37] The top CNT sensing layer can measure the gas and record it in RRAM in real-time. The stored data can be compared by input the semi-adder in the logical layer of carbon nanotube, and the calculated results can be output to the latched circuit of the underlying silicon layer. For the first time, this chip demonstrates the integration of sensing, storage, and computation in a single chip without the need for off-chip data transfer. Different from through-silicon via (TSV) as a high bandwidth memory (HBM) bus,^[12] such in situ data processing can achieve highest-throughput parallel processing, greatly reducing transmission energy consumption, while vertical stacking also saves a lot of areas. 3D chip integration is an effective way to break von Neumann bottlenecks and realize in-memory computing.

Two-dimensional material because of its extremely thin layer structure can also realize the new type of logic and memory (Fig. 1(h)).^[38] As shown, since the top and bottom surfaces can be gate-controlled, just one 2D FET can be a logic gate. With such a logic gate, adding a layer of graphene as a floating gate below it can complete real-time in situ storage. Due to the structural advantages of the two-dimensional material, such process integration is easier than silicon in nanoscale. We can see that in the same chip, in the real-time operation, the calculation results are captured and saved, thus overcoming the bottleneck between storage and calculation to complete high-throughput information processing, which provides a new idea for in-memory computing. The van der Waals heterostructures intrinsic to two-dimensional materials also broaden a new perspective to neuromorphic computing. Because the atomic-level smooth surface and high surface-to-volume ratio enable electrostatic tunability and bionic spatiotemporal hyper-connectivity between different materials, such low-dimensional materials family brings potential neuromorphic functions to artificial synapses.^[120–122] For example, a fully 2D inorganic/organic (MoS₂/PTCAD) hybrid heterojunction synapse is proposed with long-term plasticity and short-term plasticity behaviors,^[123] serving as a novel multifunctional neuromorphic device.

As the core technology of information society, IC chips can be divided into digital chips, memory chips, and analog chips according to their function and market share. Nowadays most computing chips are adopting digital logic operations. Thanks to the development of silicon-based technology, CMOS logic chips can use simple binary signals to complete complex data processing, which can perform arithmetic operations expediently with digital logic and occupy a large share in the computing market due to their high integration density and small size. Nevertheless, with the maturity of new device technologies such as RRAM and PCM, analog neural computing that has been neglected has also become feasible for large-scale applications. Because the process of the analog circuit continuous signals, the anti-interference ability and calculation accuracy are not as good as digital computing, but for specific algorithms, memory-based analog computing can achieve higher efficiency with neural network architecture.

Using Ohm’s law for multiplication and Kirchhoff’s current law for summation, vector-matrix multiplication, the foundation of neural network computing, can be easily mapped by the crossbar array, achieving in-memory analog computation.^[18] In 2009, Xia proposed that switching characteristics of RRAM could also be used as a transfer switch to realize reconfigurable logic.^[124] Meanwhile, he proposed that the memristor crossbar could be used as a brain-like synapse and the neuron of silicon-based transistor circuits could be combined to realize brain-like computing, bringing a new application direction to RRAM. In 2010, Lu first accomplished the concept of using nanoscale memristors as biomimetic synapses,^[125] and for the first time implemented the STDP learning mechanism on memristors, which drew great attention to the construction of artificial neural networks for emerging non-volatile memory devices. The essence of artificial neural network is the parallelization of memory and computing. The advent of in-memory computing in the memristor crossbar makes the neural network available by analog computing, allowing brain-like computing to take a step further. The basic units of artificial networks are synapses and neurons.^[1] Neurons, connecting by synapses with weights, can be divided into multiple layers, as shown in Fig. 2(a). These networks are usually trained by updating the synaptic weights, which can perform specific tasks such as classification after training. Implemented in the form of crossbar arrays, RRAM’s input/output signals pass through nodes made up of rows and columns. Figure 2(b) is an example of an RRAM crossbar where the matrix weights are represented as conductance.^[15] Unlike multiplicative accumulation (MAC), matrix-vector multiplication (MVM) of crossbar array can perform multiplication and summation in a single step by Ohm’s law and Kirchhoff’s law, which often takes a large amount of time and power in classical von-Neumann computers. Due to the structural advantages of resistive switch devices, high-density memory can be easily achieved by a crossbar array.^[56] New non-volatile devices, including MTJ,^[58] PCM,^[57] etc., can build artificial neural networks by the same way. In addition to two-terminal devices, emerging three-terminal transistors such as FeFET, flash, and SRAM can also be used to build neural networks. For instance, in a FeFET formed by integrating a ferroelectric capacitor into the gate of a transistor, the degree of polarization of the ferroelectric capacitor is related to the transconductance of the channel.^[36] FeFET can provide fast programming speed, low power consumption, and smooth symmetrical analog programming. Using the above crossbar array structure, FeFET can also implement matrix vector multiplication naturally, whose analog state can represent the weight of synapses in the fully connected neural network. Expect for the way how the charge is stored, flash can do exactly the same thing as FeFET with more readily manufacturing techniques. The 3D NAND flash is transformed into a accelerator for large neural networks (>100 Mb weight) with ∼ 40 TOPs/W.^[105] Due to the precise charge control from the gate dielectric, both FeFET and flash can present symmetric/linear weight update, but the flash has a slow speed and higher energy consumption for its tunneling mechanism.

Fig. 2.

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Fig. 2. Neural network demonstrations on the crossbar array. (a) Schematic diagram of a simple neural network. (b) Hardware implementation of neural network in an RRAM crossbar array. (c) A fully integrated chip with a 54 × 108 crossbar array fabricated on a CMOS substrate. (d) Schematic of the interface to the 54 × 108 crossbar array, with three read/write DACs and one ADC for each row and column. (e) The mapping of a bilayer network consisted of a 9 × 2 subarray for the PCA layer and a 3 × 2 subarray for the classification layer in the 54 × 108 crossbar array. (f) Schematic of a five-layer memristor-based CNN used for MNIST image recognition with eight 2048-cell memristor arrays. Panels (c), (d), and (e) are reproduced from Ref. [23]. Panel (f) inset is reproduced from Ref. [24].

Compared with the high energy consumption of the traditional CMOS circuit, the resistive switch device is regarded as the electronic synapse to store weight and transmit signals at the same time, so it is more conducive to exploit the analog in-memory computing with ultra-low power consumption. The two-terminal resistive switch easily participates in data processing while accomplishing the data storage, providing high data throughput that is of great significance for various AI applications. Note that conventional silicon-based computing components are still required for the resistive switch device’s potential commercialization in the near future, the resistive switch devices can be fabricated compatibly over the existing CMOS substrate due to the low thermal budget. A 54 × 108 memristor crossbar was integrated on the top of CMOS circuits including all the necessary interface circuitry, digital buses, and an OpenRISC processor (Fig. 2(c)).^[23] With two write DACs, one read DAC, and a 13-bit ADC configured at each row or column of the array (Fig. 2(d)), the fully integrated chip is highly flexible to form different desired arrays (Fig. 2(e)), allowing autonomously mapping different neural network algorithms to accomplish specific computing tasks or applications. Unlike the reinforcement to the capability of access interface above, another common way to strengthen the neural network performance is by optimizing the device fabrication process to prepare more high-yield high-performance and uniform crossbar arrays. As shown in Fig. 2(f),^[24] 8 uniform 2048-cells memristor arrays were also fabricated for the implementation of five-layer CNN to perform MNIST image recognition with a high accuracy of 96.19%, showcasing that deeper neural layers will significantly excavate the network’s computational potential.

A more biologically-inspired approach, spike neural networks (SNN),^[18] can rigorously mimic the mechanism of brain information processing. CMOS circuits have been implemented in hardwares such as IBM’s truenorth^[126] and Intel’s Loihi.^[127] However, CMOS devices are ultimately unable to achieve the fusion of memory and computing, bringing a large waste of resources. It is important to find artificial synaptic devices with analog synaptic function, while simple two-terminal memristors can accomplish similar functions with obvious reduction in area, complexity, and power consumption. Artificial neurons with leaky integrate-and-fire (LIF) function have been explored by a single memristor device.^[45] Furthermore, the lattice polarization dynamics of the ferroelectric layer in FeFET can imitate the learning rules of SNN, like spike-timing-dependent plasticity (STDP).^[35] Novel low-dimensional materials also pave the way for SNN synaptic devices,^[128] such as CNT synapses applied for unsupervised learning with an STDP scheme.^[129] Figure 3 shows the timeline of neural network hardware progress through memory devices. Thanks to the efficient algorithms like the well-known back propagation, applications for DNN can be easily implemented in hardware by these new memory technologies. However, most researches on the scaling-up of SNN devices still stay in simulations. Demonstrated experiments have shown that although neuromorphic computing is at an early stage of its technological maturity without large scale implementation, it represents a promising long-term direction for AI chips and general in-memory computing.

Fig. 3.

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	Fig. 3. Timeline of major hardware implementation on neural network towards to neural-inspired computing.

Since the mechanism of conduction depends on the change of microscopic components, resistive switch devices such as PCM and RRAM will inevitably have certain variances that are often regarded as disadvantageous factors. In the process of IC manufacturing, we strive to reduce the variances to the smallest. However, there are great advantages in realizing the identification of specific objects by the random differences inherent in such solid-state devices. This property of randomness is almost identical to the principle of bio-identification technology, which is defined as physical unclonable function as a hardware. RRAM-based PUF, for example, not only takes advantage of the variability of integrated circuits in the manufacturing, but also uses the randomness inherent in the conductive mechanism of RRAM.^[48] This inherent randomness originates from the oxygen vacancies inside the insulating dielectric between the top and bottom electrodes of the RRAM. When a conductive filament is formed and broken, the nanoscale gaps between the oxygen vacancies will inevitably change from different devices (device to device), even between different switching cycles of the same RRAM cell (cycle to cycle), and these changes can be expressed through the RRAM resistance or current. Therefore, compared with other technologies, RRAM possesses more random possibilities. The first reconfigurable PUF chip based on RRAM has been designed (Figs. 3(a) and 3(b)),^[130] which has significantly improved reliability, uniformity, and chip area compared to previous work, and has unique reconfigurable capacity. SRAM-based PUF is currently the most commercially available PUF,^[131] which has the advantages of easy implementation and good compatibility, but it cannot effectively resist photoelectric attack and has inherent deviation. Relatively speaking, NVM-based PUFs can effectively balance the advantages and disadvantages above, achieving low original bit error rate while possessing better resistance to physical attacks and reconfigurability. Benefitting from the lower cost, easier integration, the nanometer size, and compatibility with CMOS technology, it is a very suitable material for PUF research and has a high research value in term of hardware security that has good development potential.

Although variability is a fatal flaw for traditional computing, but it is useful in stochastic computing, where it can be used to generate random numbers. Random numbers generations (RNG) are significantly important for stochastic computing,^[132] data encryption, and neuromorphic computing.^[133] Using the randomness inherent in RRAM, a true random number generator can be prepared, which is more stable and reliable than other pseudo-random number generators that need to provide seeds. Different experiments^[134,135] have shown how to generate random numbers through memristors, one of which utilizes the stochastic delay time by exploiting switching variability to improve the quality of the generated random numbers (Fig. 4(c)).^[136] A bias voltage slightly below the threshold value is applied across the RRAM device. After waiting for a period of time, the current through the device will suddenly increase, meaning that the RRAM is turned on, and then the device is reset back to the off state. Such a period of time for an RRAM to reset switch is stochastic, because the transition of this state is driven by thermodynamics involving the mobile transmission of oxides and ions. Theoretically, such a distribution of delay time T should satisfy the Gaussian distribution. Based on this time, we can divide by a small enough time interval Δt to guarantee a 50% probability of generating either odd or even number (corresponding to 1 or 0). A stream of random numbers can be obtained continuously by giving the same voltage and time pulse. For instance, in-memory stochastics computing only needs one AND logic gate to complete the multiplication of two fractions (Fig. 4(d)).^[133,137] By using RRAM to generate random numbers, the independence and authenticity of the random numbers can be guaranteed and the accuracy of stochastic computing is improved. It also eliminates the conversion process between random numbers and binary numbers, allowing for simpler arithmetic operations that are more efficient than traditional binary-based stochastic computing. In addition to RRAM, MRAM devices can also be used to generate random numbers with better endurance and faster switching speed. Inspired by the principle of neural network, scientists have developed a new type of hardware that enables factorization, which is one of the mathematical underlies of modern asymmetric encryption and very important for existing encryption systems. The manufacturing process and usage of such stochastics magnetic circuit hardware (Fig. 4(e))^[138] based on MRAM are simpler than those for the current popular quantum computing. Now it needs only 8 bits to perform factorization on number 945. Stochastic computing has certain applications in fault-tolerant neural networks,^[139] image process,^[140] and decoding of check codes,^[141] where NVM-based random number generation makes in-memory stochastic computing more feasible with simple circuit layout and reconfiguration.

Fig. 4.

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Fig. 4. Stochastic applications based on memory technologies. (a) Top view of an RRAM PUF chip with the key parameters and cell layout. (b) Comparison of performance between the RRAM PUF and other technologies for PUF. (c) Schematic of generating random numbers with the delay time from the memory devices. (d) Diagram of using one AND gate to complete fractional multiplication with generated random number streams. (e) Factorization using stochastic magnetic tunnel junctions. Left: printed circuit board of the interconnected MTJ circuit. Right: electrical schematic of a stochastic MTJ with external circuit components. Panel (a) is reproduced from Ref. [130]. Panel (c) inset is reproduced from Ref. [16]. Panel (e) inset is reproduced from Ref. [138].

Digital computing is the main function of traditional silicon-based IC chips, and its ability to solve complex computing tasks through basic digital logic has brought a lot of convenience to human life. Compared with the analog computation, published literature is scarce about its array-level experimental demonstration. In order to break through the existing bottleneck of von Neumann while ensuring the calculation accuracy, it is necessary to realize digital logic calculation for general-purpose in-memory computing. According to the number of states stored in the storage unit, the digital calculation can be divided into binary logic calculation based on switching characteristics and multi-bit calculation based on polymorphic storage. From binary to multi-bit, hybrid precision computing can be achieved in in-memory digital computing.

Since the invention of the transistor, switching transistors have a great advantage in binary computing through continual shrinking of feature size, becoming the most fundamental method of information processing technology today. In order to achieve digital calculations with low energy consumption and high area efficiency, new digital calculation concepts such as quantum dots^[142] and even single atoms^[143] have been proposed one after another, but these new experimental demonstrations have not yet achieved a good control of voltage and current on individual units. Instead, the new material devices like carbon nanotubes^[118] and two-dimensional material^[119] transistors bring out the promising performance in these respects. Profit from the flawless in the material lattice surface, both carbon nanotubes and two-dimensional material transistors can be heterogeneously integrated in nanoscale. Therefore, a memory cell is conveniently stacked on the logic transistor formed by such new materials to accomplish in situ memory. The three-dimensional integrated in situ memory chip just vertically stacks the bitwise RRAM cell on the top of carbon nanotubes field-effect transistors (CNFETs) so the half-adders constructed by the CNFETs are able to access the stored values immediately to complete conventional binary computing (Fig. 5(a)),^[37] in which way the memory cost is largely reduced while maintaining the efficiency of binary computing. A novel dual-gate transistor made by two-dimensional materials is also invented for one-transistor binary logic and in situ memory. When both top gate and back gate are used as inputs, the charges in the floating-gate layer are attributed as the stored value to participate in the binary computing (Fig. 5(b)).^[38] Such a prototype demonstration using one transistor to fulfill in-memory binary computing can achieve highest-throughput parallel processing and reduce transmission energy consumption, highlighted for the area-efficiency and multifunction.

Fig. 5.

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Fig. 5. Binary digital computing based on memory technologies. (a) Schematic of the classification accelerator constructed by carbon nanotubes field-effect transistors. Left: a monolithic 3D cell for the three-dimensional integration nanosystem. Right: component diagram of the CNFET computational layer. (b) In situ memory logic in a 2D vertical dual-gate transistor. Left: schematic of the 2D vertical dual-gate transistor structure. Right: demonstration of the logic behavior in the 2D vertical dual-gate transistor with a floating gate. (c) Stateful logic enabled by resistive switch devices. Upper: basic material implication (IMP) logic implementation. Bottom: NAND logic implementation method based on IMP and FALSE logic. (d) Full adder based on stateful logic computing of resistive switches. Left: circuit diagram and the corresponding equivalent networks of a full adder. Right: the truth table of the full adder logic. Panel (a) is reproduced from Ref. [37]. Panel (c) is reproduced from Ref. [50]. Panel (d) is reproduced from Ref. [21].

Resistive switch devices such as RRAM and PCM show many advantages of implementing binary calculations. With the simple structure, it is easy to achieve crossbar integration and directly reconfigurable under the control of current and voltage. The high and low conductances can be used to denote the logic variables ‘0’ and ‘1’, respectively. More importantly, it is tantalizing for their facilitating miniaturization and non-volatile memory. Taking RRAM as an example, non-volatile binary logic can be achieved as ‘stateful’ logic.^[50] If the resistance is also applied as the input variable so that the physical variable of input and output is uniform, such logic operation is called stateful logic. A basic stateful logic cell usually requires multiple devices to be connected in a certain way. The resistance divider between the devices will determine the final output result. There are two different stateful logic methods (IMP^[50,144] and MAGIC^[145,146]) and we take IMP for example. The IMP basic logic is composed of two identical memristors P, Q and a voltage dividing resistor R_G, as shown in Fig. 5(c). Among them, R_G is much larger than the low resistance of the memristor, but much smaller than the high resistance of the memristor. The two input variables p and q are represented by the resistance values of memristors P and Q, respectively, while the output variable q′ is represented by the final resistance value of q after applying the operating voltage. Therefore, the input variables p and q are stored in devices P and Q in the form of resistance values. During the logic operation, the operating voltages V_cond and V_set are applied to the signal side of devices P and Q, respectively, and the resistor R_G is grounded. When the input variable p = 1, the common wire potential is about V_cond. At this time, the divided voltage of the device Q is not enough to change the state of the device, so the output q′ = q. When the input variable p = 0, the resistance value of memristor P is high, the common wire potential is about 0, and the divided voltage of the device Q is about V_set. This voltage has reached the condition that the device changes from a high resistance state to a low resistance state, so the final resistance state of the device Q is low and the output result q′ = 1. The truth table is shown in Fig. 5(c). It can be seen that this logic unit implements the material implication logic (IMP). IMP and false logic can constitute a logically complete set, based on which all 16 basic Boolean logic functions can be implemented. The corresponding logical expressions need only be expressed as a combination of IMP and FALSE, and then realized through multiple cycles. In a similar way, we can also show the implementation of the NAND logic. A complex full-adder is also composed by cascading more memristors but with more complicated operations (Fig. 5(d)).^[21] Although the physical quantities of stateful logic inputs and outputs are consistent and can be easily cascaded, a logic unit requires the connection of multiple devices, which causes the problem of connection disturbance. It requires higher device uniformity and more circuit elements other than memristors. Besides, the specific logic operating voltage also increases the complexity of the peripheral circuits. When the physical variables of input and output are not uniform, such logic operation is called non-stateful logic^[53] (input by voltage but output by resistance). A common way of implementing non-stateful logic is based on the bipolar/complementary memristors. Using this non-stateful logic, 14 basic Boolean logics except XOR and XNOR can be implemented in 3 steps in a single memristor, but additional steps are required to rewrite the results back into the device, given the destructive reading mode. The advantage of non-stateful logic is that a single device can be seen as a logic unit to implement a complete and efficient Boolean logic, achieving in-memory computing. However, due to different physical values of input and output, the peripheral circuit is also required to convert the signal output, which greatly reduces the advantage of in-memory computing and increases the time and space complexity of logical operation.

In addition to memristors, other resistive switch devices, such as PCM^[82] and STT-MRAM,^[97] also can achieve similar non-volatile logic operations, which shows the universality of non-volatile logic storage and calculation. Compared with the conventional CMOS logic, non-volatile logic uses the same circuit structure to implement reconfigurable logic by applying different voltages, not only non-volatile, but also flexible reconfiguration. However, the required steps increase with the increase in functional complexity, sacrificing a certain computing efficiency and the power consumption will increase. On the other hand, the traditional silicon-based in-memory computing devices, such as flash, FeFET, and SRAM, can complete Boolean logic and save the data in one operation based on the traditional CMOS logic operation,^[108,114] though still sacrifice a certain area and power consumption, which is acceptable for the energy consumption cost by data transporting. Moreover, these novel binary computation technologies are all in the preliminary research stage with many possibilities for improvement. The in situ storage realized by the new material carbon nanotubes and two-dimensional materials can also integrate the memory unit on the computing cell through 3D stacking without changing the logic operation of the conventional transistors, while maintaining the advantages of traditional binary logic it can also perform high-speed parallel storage, even if the related research is still in the early proof-of-concept stage.

The optimization and advancement of memory technology help to realize the storage of more states than 0 and 1, making multiple states computations possible. For devices with conventional memory function, the binary representation is naturally easy to implement because there are only two states: 0 and 1. Part of the reason for using binary is that the states of the memory are limited. The higher degree of freedom of computation puts higher requirements on the memory device, meaning that the device unit should store more states, which is different from the binary switching characteristics. At present, device technologies that can implement multiple state storage include RRAM,^[45] PCM,^[52] flash,^[147] and so on. Usually, a suitable electrical signal such as an accumulated pulse is applied to these memory devices, and the resistance of the device evolves accordingly. By reading out the resistance value at the appropriate time, the corresponding input electrical signal calculation is done. For example, the resistance transformation of PCM is determined by the gradual crystallization of its phase transition layer in the non-crystalline state. Under the continuous stimulation of a voltage pulse, the more crystallization, the lower resistance, so it has phase change accumulation characteristics. As shown in Fig. 6(a),^[53] in order to complete the decimal addition, the number of voltage pulses of the first addend is input first, followed by the second addend pulses. The two addends are accumulated in the PCM in the form of voltage pulses. A certain number of additional pulses need to be sent until the threshold is reached by a program/verify loop. If the threshold is set at ten pulses, the number of pulses required to reach the threshold can be used to derive the decimal calculation result, for example, like (2 + 5) = (10 – 3) = 7 (Fig. 6(a)). Based on such accumulated characteristics, the same schemes can be used for subtraction, multiplication, and division easily while storing the results at the same time.

Fig. 6.

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Fig. 6. Multiple-state digital computing based on memory technologies. (a) Schematic of decimal summation operation with an accumulative PCM. (b) Factorization of a number with the parallel PCM devices. (c) Flow process of temporal correlation detection achieved by accumulative PCM devices. (d) Experimental demonstration of 1000 × 1000 PCM devices to map the correlated processes. Panels (c) and (d) are reproduced from Ref. [148].

Other fascinating applications of in-memory computing that take advantage of the accumulative behavior are prime number decomposition^[53] and temporal correlations.^[148,149] Finding a factor (M) of the specific number (N) is similar to the 10-based addition. First a specified resistance threshold is set after applying the number of M pulses. Second, the device needs to be RESET every time the resistance reaches the specified threshold while the total number of N pulses are applied to the device sequentially. In the end, if M is a factor of N, the final state of the device will reach the threshold, otherwise it is not. Multiple configured PCM devices can be fed in the same number of N pulses in parallel to validate more different M factors simultaneously (Fig. 6(b)).^[80] In the application of temporal correlations, unsupervised learning can be achieved between binary random processes of the devices.^[148] Every PCM device is treated as a single process and reset initially. When the process is 1, the corresponding device is applied to a SET pulse whose amplitude is proportional to the sum of all 1 processes in this iteration. In this way, as the iteration increases, the conductance of the device corresponding to the process with a high correlation will increase, while the conductance of the device corresponding to the process with a low correlation will remain at a low state. Finally, binary classification can be completed through such cumulative and the high conductance reflects the strong correlation result (Fig. 6(c)). An algorithm has been demonstrated on 1000000 PCM devices (Fig. 6(d)), and such binary classification not only avoids device variability and nonlinearity, but also reduces computational complexity. Binary classification can also perform operations similar to neuromorphic rules. PCM accumulates the input pulse signal each time, but when the integral reaches a certain threshold, the conductance suddenly becomes large enough to send the pulse signal, which can imitate the LIF model and hopefully realize SNN.^[44,87] However, each time the PCM device reaches the pulse threshold, an additional RESET operation is required to restore it to the off state, while RRAM does not. Compared with SNN neurons composed of silicon-based CMOS, PCM and RRAM are easy to achieve miniaturization.

Unlike simple binary memory, non-volatile computing places higher requirements on the performance stability of individual devices, because the requirements for the uniformity and cycle durability of the devices are higher for forcing the computation on memory. The most important issue in device research is uniformity, from device to device or cycle to cycle. Regardless of the two-terminal or three-terminal devices, the complexity and maturity of manufacture will greatly affect the uniformity between different batches even in the same batch of devices. Therefore, the technology based on the traditional silicon-based CMOS process has a great advantage on the advance of manufacture, while the new device technology is still needed to explore the more mature technologies in preparation. The difference in device mechanisms also greatly affects the issue of uniformity. For resistive switches, changes in the material properties of the resistive layers determine the transition of the device state, which is stochastics. It may be acceptable at a sufficiently large size, but due to the randomness of the ions when the device is small enough, movement or thermal activation of defects can cause fluctuations in device parameters, thereby reducing uniformity. For digital computation, the accuracy of the calculation results is very important, so the random fluctuations will reduce the calculation reliability. For analog computation, the computational disturbance caused by the randomness of microscopic particles can be used to avoid falling into the local optimal solution, so the analog computing has a certain tolerance for the variation. In particular, stochastic computing just takes good advantages of this kind of parameter fluctuation randomness to achieve truly random generation, and it is necessary to ensure that the variations are sufficiently stochastic. Of course, the parameters of each device still need to guarantee a reasonable range. The optimization for uniformity is also one of the hot research topics in the world, especially for memristors, such as using interface type memristors to replace conductive filament type memristors,^[150] increasing the switching ratio to compensate for the resistance fluctuation, introducing dislocation defects or local doping to limit the position of the shape of the conductive,^[151,152] etc.

Due to the high frequency of calculation, the devices need to undergo a large number of repeated operations, which is a big test for the stability of the device. The current response during the switching process (that is, the stored procedure) inevitably produces joule heat, limiting the lifetime of the devices. The lifetime varies for different device technologies. MRAM requires only a small amount of current to operate so it can be repeated up to 10¹⁴ times.^[94] The endurance of the memristor depends largely on the current in the working state. Uniformly based on the traditional silicon-based MOS process, the cycle durability of flash and SRAM is quite different, because flash requires large power consumption to erase and write, making its lifetime almost the shortest, while SRAM can theoretically perform countless repeated operations. In order to maximize the potential of the device, the selection of its materials and optimization of its structure are critical. For example, for memristors, selecting materials such as tantalum oxide and hafnium oxide from a resistive material system with only two stable chemical phases can effectively improve the cycling durability.^[28,153] Moreover, suitable operating voltage,^[154] electrode material selection,^[155] and algorithm design optimization^[156] are also helpful to improve endurance. A decent retention is the basic ability of these memory technologies, but in nanoscale the conductance state of the devices tends to drift with time, temperature, and voltage bias, which is prone to cause computing inaccuracy. The influence of such drift can be alleviated to a certain extent by selecting the device with a large I_on/I_off ratio.

Apart from variability and endurance, factors affecting the device include read/write speed, power consumption, number of states, symmetry, and linearity. Different device technologies have their own strengths and weaknesses in these aspects (Table 1).^[157] RRAM can achieve up to hundreds of conductance states,^[158] but it is not as good as PCM in terms of symmetry and linearity.^[159] The volatile SRAM has a relatively large area and power consumption, but in-memory computing under the non-von Neumann structure naturally eliminates the transmission energy between memory and calculation, so the power consumption of a single SRAM cell is still acceptable, since the overall power consumption is still lower than the von Neumann architecture. A 351 TOPs/W SRAM macro was prepared in 7 nm technology node for machine-learning applications.^[117] Hence, in-memory computing based on SRAM is the best choice for commercial scheme by far. Compatible with the MOS manufacturing process, flash is also more mature than other memory devices and easy to linearly program. But the major disadvantages of flash are the limited endurance, large programming power, and low speed, so flash with sufficient large storage array is suitable for the inference computing instead of the training process in the edge devices. For example, a 3D NAND flash convolutional core was proposed for deep neural networks.^[33,105] Specific applications also have different requirements for devices. In digital computing like stateful logic application, fast and high endurable but low power switching characteristic is particularly demanding.^[160] For neural networks applications, symmetry and linearity are especially significant in weight update to ensure the learning accuracy.^[161,162] A hybrid hardware–software neural network demonstration based on PCM can only achieve the accuracy of 82% without enough symmetry and linearity while the software experiments maintain the accuracy of 97%.^[161] Different memory technologies have their own strengths, so researchers should apply them with trade-off according to the appropriate needs. In order to facilitate the device design for neural network applications, a simulation platform called NeuroSim is developed,^[163] which considers the non-ideal factors from device level to circuit level and benchmarks the trade-offs between different memory technologies. According to the analysis of NeuroSim, 6-bit weight and 1–2-bit weight are respectively enough to meet the needs for online training and offline inference. Endurance and variation are the main problems of these memory technologies, which need to be overcome at device level at present. Great progress can be made for in-memory computing if these two challenges are solved.

Table 1.

Table 1.

Table 1. Comparison of Pros. and Cons. between different memory technologies. . Technology RRAM PCM STT-MRAM Flash FeFET SRAM In situ memory Material metal oxide chalcogenide magnetic insulator ferroelectric material silicon 2D materials/nanotube Switching mechanism vacancy Joule heating spin injection charge trap electric polarization field effect confinement In situ access Pros. low voltage/easy structure endurance/multi-bit endurance/low voltage low cost/multi-bit speed/multi-bit fastest highest parallelism Cons. drift/variability power small on-off ratio speed/endurance instability area/volatile immature process

Table 1. Comparison of Pros. and Cons. between different memory technologies. .

Traditional silicon based CMOS technology has been a mainstream technology for the past 50 years due to its advantages of miniaturization for integration. Large-scale integration is the only way for in-memory computing to go beyond the laboratory and into real life applications. In-memory computing technologies based on flash, SRAM, and FeFET are perfectly compatible with the current CMOS process, allowing the corresponding technologies to continue on the current Moore’s law path. Although there is still a great debate about the slowing down or even the end of Moore’s law, in-memory computing can greatly reduce the transmission power consumption for the problem of memory wall, bringing a certain increase in efficiency to the integrated chips. So exploiting the advantage of silicon-based technology is a feasible solution for large-scale in-memory computing. Using the most advanced 7 nm technology, an SRAM macro for machine learning is built with powerful computation. In addition to continued scaling to improve performance, silicon-based leading technologies can also be transferred to other memory devices’ compatible processes, boosting their productivity. For example, extreme ultraviolet lithography is helpful for mass production of nanoscale cross array, while most physical vapor deposition (PVD) and atomic layer deposition (ALD) techniques can also be used to produce switching layer, dielectric layer, and metal layer with excellent conformity, accurate thickness uniformity, and component control.

Because of the simple device structure, the two-terminal resistive devices can easily be made into crossbar arrays, which have been prepared to achieve certain functions. Some of them are separate-array chips that work with external processing chips,^[24] while others are manufactured by fusion with CMOS chips.^[23] The current level of arrays can only deal with simple tasks. To further handle complex tasks, the size of arrays needs to be enlarged, whereas some problems will be encountered at this step. Although the crossbar array has the advantage of a simple manufacturing process, when reading the resistance value of the device, the existence of leakage current paths introduces parallel current paths, which may cause incorrect reading results and bring additional power consumption problems. Meanwhile, the crosstalk problem caused by the highly parallel writing of the array will also affect the resistance of unselected devices to a certain extent.^[164] Especially for digital logic calculation, since it requires accurate reading of each independent unit, the existence of leakage current will have a great limitation on the logic operation function. All nodes need to be opened when the crossbar network is used for inference in analog computing, so the problem of leakage current does not exist, but the precise control of changing the weight of each node still needs to be avoided as much as possible during the training process. The leakage problem will become more serious as the size of the array increases, limiting the expansion of the array, and thus restricting the increase in functional complexity. The current solution to this problem includes applying a protection voltage during the operation of the array, making the memristor itself non-linear through device optimization, and striding devices in series on the memristor unit to form 1D1R, 1S1R, and 1T1R structures.^[165–167] But the cascaded structure will make the unit area larger, especially the 1T1R structure. Resistive switch devices can be made to have very small feature sizes, which is also beneficial to reduce the required area to achieve the expansion of the array size, but this also introduces the problem of line resistance and capacitance. Since the interconnect metal wire is not an ideal conductor, parasitic capacitance resistance will bring RC delay and line resistance voltage division. On the one hand, it will increase the circuit delay. At the same time, the uneven voltage distribution may make the devices farther away from the power supply voltage and not work properly, resulting in a decrease in the reliability of operation.^[168] In order to alleviate this problem, we can increase the width and thickness of the metal interconnect,^[169] increase the access point of the power supply and ground wire,^[170] exploit the novel materials like carbon nanotubes and graphene,^[171] etc., all of which will of course have area consumption. Another option is to divide the array into many small arrays, connected horizontally in two dimensions or stacked in three dimensions, so that the effect of the resistance and capacitance in such small array can be eliminated. In the face of these challenges encountered in large-scale array integration, how to compromise area efficiency and computing efficiency is the main contradiction. The benefits of crossbar implemented by two-terminal devices is that it can be stacked in 3D, which undoubtedly can relax the requirement of area efficiency,^[172] but it also needs to improve the preparation process.

Methods of stacking computing and memory together utilizing two-dimensional materials or carbon nanotubes are also a potential solution to the problem of memory-accessed bottleneck. By taking advantage of the fact that both the upper and lower surfaces of the two-dimensional materials can be used as input channels, and adding a floating gate as the storage layer, a transistor can be used to realize OR or AND logic gate, which has high area utilization while reducing the transport bottleneck.^[38] Stanford’s ILV (inter-layer via) 3D IC system is also moving beyond the university laboratory toward commercialization and large-scale application.^[37] Unlike TSV 3D IC, ILV 3D IC does not stack multiple chips by packaging, but directly implements multiple chips (monolithic 3D IC) on a single wafer. Carbon nanotubes are connected to the underlying CMOS via the interlayer dielectric layer (ILD), enabling instant access to the CMOS circuit calculated results. ILV can achieve the interconnection density that 3D IC can achieve, easily reaching the feature sizes down to tens of nanometers, thus greatly improving the performance of the overall chip system. But the integration scale of these new materials is still too small for current SoCs. If carbon nanotubes and two-dimensional materials want to walk into the mainstream and promote large-scale manufacturing yield, the design of standard cell library for these new devices, as well as the EDA tools and processes,^[173,174] is needed, all of which are actually a problem of design methodology and industrial ecosystems.

To further explore the practical application of the in-memory computing, peripheral control circuits and system-level algorithms are the other two key issues that hinder the implementation of system-level chips. The peripheral circuits of most prototype concept devices are based on mature CMOS technology, which is friendly to flash, SRAM, and FeFETs compatible with silicon-based processes, but not necessarily compatible with resistive switch devices and new material devices for non-traditional manufacturing processes. Because the research of in-memory digital logic computing mainly stays at the device level, there are basically no large-scale arrays at present, and the peripheral circuit and algorithm applications at the system level are still blank, which needs more research to further realize the application. Here we mainly discuss the system-level peripheral circuits and algorithms of in-memory analog computing. Most of the research on analog computing focuses on the integration of device arrays,^[25] and rarely explores the optimal design of peripheral,^[23] whether it is an independent device array or an array chip integrated with silicon. Due to the need for precise programming control over the storage state (usually the conductance state) of each device, the most commonly used and important peripheral circuits are digital-to-analog converters and analog-to-digital converters.^{[23–25,175,176]} The results of analog calculations still need to be transmitted to other digital peripheral circuits for integration processing and then feedback into the arrays, which already accounts for 60% energy consumption of the overall system, thus requiring low-power ADCs and DACs.^[177] Because the matrix-vector product that originally consumed the most energy in the algorithm can now be completed in one step in the crossbar array, it seems that the multi-step processing of the peripheral circuits in the algorithm is more redundant, and the proportion of energy consumption in this part is also relatively large. Considering the various random migration processes, the device units have high mismatches in the practical manufacturing process. In order to compensate for the shortcoming of these mismatches, when completing the multi-bit calculation, additional anti-maladjustment and mismatch compensation circuits are usually required, or compensation can be performed by online learning to update neural network parameters. One solution to alleviate the requirement for peripheral circuit is to improve the robustness of the arrays. By combining high-performance crossbar arrays with a hybrid-training method, the implementation of five-layer CNN to perform MNIST image recognition with a high accuracy of 96.19% was achieved in eight uniform 2048-cells memristor arrays, providing a feasible scheme for greatly improving the efficiency of CNN (Fig. 2(f)).^[24] Besides, how to use the peripheral circuit to read rows and columns efficiently also needs to be carefully designed. To better unleash the arrays’ flexibility to perform MVM operations, 3 DACs and 1 ADC are interfaced with each row/column, allowing bidirectional and full transpose operation of the crossbar (Fig. 2(d)).^[23] The optimization of peripheral circuits is highly dependent on the algorithm adopted by the system. For example, in the most commonly used DNN analog computing, the results obtained will select whether the external circuit is a comparator, a shift register, or a lookup table according to the step function adopted by the algorithm.^[17] Therefore, the peripheral circuit needs to be combined with calculating kernels to optimize the energy efficiency and speed as a whole system. It is important to note that traditional silicon-based ADCs and DACs have also reached the saturation stage, leaving little room for energy efficiency and area optimization.

If the algorithm can reduce or optimize data process steps other than the matrix-vector product, the energy consumption and required area will be reduced even more. The closer the hardware is to the algorithm, the better the application of the algorithm will be.^[19] As the most explored memory technology for in-memory computing, RRAM has been used to prepare many experimental demonstrations for artificial neural network applications from single-layer perceptron,^[39,40] sparse coding^[43] to reinforcement learning^[25] and convolution neural network^[24] (Fig. 3). Deep neural networks are now so popular because of their algorithmic applicability, where the algorithm steps can be easily mapped by a hardware that performs MVM operations excellently. A three-dimensional memristor crossbar circuit is also fabricated to further explore more parallelism and capability of memory arrays for complex neural networks.^[172] The emerging SNN is closer to the human brain’s thinking mode than DNN, but SNN algorithms are rarely implemented in arrays at present. Theoretically, SNN has more intelligent advantages than DNN to process voice and video information, but it is still difficult to map the algorithm to the device level.^[18] Designing a hardware that cooperates with SNN rules is a big step towards neuromorphic computing, which will unleash even more unimaginably applicable computing. Unlike maturely developed DNN, SNN still lacks an efficient and streamlined hardware implementation. At least for now how to implement system-level algorithms based on SNN array chips is the key research direction.